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The Open Memory Initiative (OMI)

Memory module design sits behind NDAs. OMI builds a DDR4 UDIMM reference design anyone can study, modify and manufacture, with every decision recorded first.

Last updated: October 1, 2026

Why Open Memory?

The memory module industry lacks transparency. From schematic references to signal integrity guidelines, much of the knowledge is locked behind NDAs or proprietary documentation. The Open Memory Initiative was founded to change this.

OMI is building a fully transparent, reproducible DDR4 UDIMM reference design that anyone can study, modify, and manufacture. OMI v1 has reached a complete KiCad schematic that passes ERC with zero violations and no waivers; no board has been laid out or built yet (OMI README).

The Decision Documents Behind OMI v1

OMI records its major design decisions in documents that weigh the options, state the choice and its rationale, and mark it locked. The DDR4 and UDIMM choices were locked on 2025-12-26, a day before the first KiCad file entered the repository.

DDR4 UDIMM Form Factor Selection

Context: OMI's form-factor document weighs two DDR4 modules, the full-size UDIMM and the SO-DIMM. DDR4 itself had been chosen over DDR3 earlier the same day, in issue #1.

Decision: UDIMM, for probe access during validation, routing room for signal integrity margin, desktop BIOS visibility, contributors' access to desktop systems, and clearer teaching of routing and PDN design. SO-DIMM is rejected for v1 only.

Host-Provided VREF

Context: Stage 7.1 had to choose between taking VREF from the host through the edge connector and generating it on the module.

Decision: Host-provided, locked on 2025-12-27 for lower schematic complexity, fewer analog failure modes in a first design and clearer bring-up behavior (VREF decision). No divider, buffer or regulator may create VREF on the DIMM, whose job is distribution and local decoupling.

Documentation-First Methodology

Context: Defining the development workflow for hardware design.

Decision: How OMI Is Engineered orders the work as system intent, architecture, constraints, implementation, validation and hardware, with every stage protecting the one before it. Each decision document is written before the schematic that depends on it.

Design Process

Power Distribution Network (PDN)

OMI's 288-pin edge map takes four supplies from the host, VDD (1.2 V), VPP (2.5 V), VTT (0.6 V) and VDDSPD, plus the VREFCA reference. OMI v1 regulates none of them on the module. The DRAMs' VDDQ balls join the VDD net, since a DDR4 card edge has no VDDQ pin.

Decoupling is written down as a strategy, but the schematic places no capacitors yet. Their values and placement are deferred to Stage 10, layout and SI/PI guidelines, which has not started.

Address/Command/Clock

OMI's schematic draws each address, command and clock signal as one net from the edge connector to all eight DRAMs, a simplified star chosen to keep the sheets readable and reviewable (topology decision). Fly-by, the DRAM-to-DRAM daisy chain that JEDEC routing recommends, stays the intended board topology. The same decision defers it, along with length matching and termination, to layout, which has not started.

Data Byte Lanes

In OMI's schematic each of the eight byte lanes carries 8 data bits (DQ), a differential strobe pair (DQS) and the shared DM/DBI_n pin, and each lane goes to its own DRAM. OMI's length-matching constraints ask for tight matching inside a lane and only loose matching between lanes, because each lane is trained independently. No trace has been routed yet.

Tooling: spdr

SPD, the small EEPROM every memory module carries to describe itself, is where a module's identity, timings and vendor profiles live. Firmware reads it to configure the memory controller before the RAM is used, which makes decoding it correctly a prerequisite for validating any module design.

spdr is OMI's answer: a zero-copy, no_std DDR5 SPD (JESD400-5) decoder and semantic linter. It decodes the identity and base configuration, base CRC, JEDEC base timings, UDIMM module-specific block and manufacturing data, plus the Intel XMP 3.0 and AMD EXPO overclocking profiles, each checked against its own CRC. It then goes past the checksum to lint what the bytes actually mean, flagging modules whose structure or timings are internally inconsistent even when their CRC is perfectly valid.

Because it allocates nothing and needs no standard library, it can be embedded in firmware and UEFI code as well as run on a host.

It ships under Apache-2.0 as two crates: spdr, the library, and spdr-cli, which installs the spdr command-line tool. Unbuffered modules (UDIMM) are complete; SODIMM, RDIMM and LRDIMM are deferred.

Educational Content

OMI's documentation opens with five teaching chapters, numbered 00 to 04 and holding 20 documents. They entered the repository on 2025-12-22, five days before the first KiCad file:

Tech Stack

Where OMI v1 Stops

OMI v1 stops at a complete schematic: a 288-pin card edge, eight DRAMs, the SPD EEPROM and eight ZQ resistors, all footprinted, with a netlist, BOM and PDF exported only from an ERC-clean design (README). What stands between that schematic and verifiable hardware has not started: