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The Open Memory Initiative (OMI)

Memory module design sits behind NDAs. OMI builds a DDR4 UDIMM reference design anyone can study, modify and manufacture, with every decision recorded first.

Last updated: September 2, 2026

Why Open Memory?

The memory module industry lacks transparency. From schematic references to signal integrity guidelines, much of the knowledge is locked behind NDAs or proprietary documentation. The Open Memory Initiative was founded to change this.

OMI is building a fully transparent, reproducible DDR4 UDIMM reference design that anyone can study, modify, and manufacture.

Architecture Decision Records

Every major design decision is documented through Architecture Decision Records (ADRs) before implementation begins. This methodology ensures traceability, reproducibility, and educational value.

ADR-001: DDR4 UDIMM Form Factor Selection

Context: Choosing between SO-DIMM, UDIMM, RDIMM, and LRDIMM form factors.

Decision: UDIMM was selected as the reference platform due to its ubiquity in desktop and entry-level server systems, simpler topology (no register buffer), and lower barrier to entry for contributors.

ADR-002: KiCad as Primary EDA Tool

Context: Evaluating EDA tools for schematic capture and PCB layout.

Decision: KiCad was chosen for its open-source license, active community, and growing industry adoption. This ensures the entire toolchain remains freely accessible.

ADR-003: Documentation-First Methodology

Context: Defining the development workflow for hardware design.

Decision: All design work follows a staged approach: research, document, design, validate. Architecture decisions are recorded in ADRs before any schematic work begins.

Design Process

Power Distribution Network (PDN)

The DDR4 UDIMM requires multiple voltage rails: VDD (1.2V), VDDQ (1.2V), VPP (2.5V), and VTT (0.6V). The PDN design focuses on decoupling strategy, plane impedance, and bulk capacitor placement.

Address/Command/Clock

The address, command, and clock routing follows JEDEC timing specifications with careful attention to fly-by topology for clock and address signals. Impedance matching and length matching are critical in this domain.

Data Byte Lanes

Each data byte lane consists of 8 data bits plus a DQS strobe pair. The routing strategy prioritizes matched lengths within each byte lane while allowing controlled skew between byte lanes.

Tooling: spdr

SPD, the small EEPROM every memory module carries to describe itself, is where a module's identity, timings and vendor profiles live. A memory controller reads it before it can trust the RAM, which makes decoding it correctly a prerequisite for validating any module design. The tooling that does so is largely proprietary.

spdr is OMI's answer: a zero-copy, no_std DDR5 SPD (JESD400-5) decoder and semantic linter. It parses an SPD image in nine stages: identity, CRC verification, timings, manufacturing data, and the vendor overclocking profiles (Intel XMP and AMD EXPO). It then goes past the checksum to lint what the bytes actually mean, flagging modules whose structure or timings are internally inconsistent even when their CRC is perfectly valid.

Because it allocates nothing and needs no standard library, it runs in firmware and UEFI contexts as well as on a host.

It ships under Apache-2.0 as two crates: spdr, the library, and spdr-cli, the command-line binary. Unbuffered modules (UDIMM) are complete; SODIMM, RDIMM and LRDIMM are deferred.

Educational Content

OMI includes 10+ educational chapters covering:

Tech Stack

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